Modified decimal matrix codes for error detection in memory using pipeline architecture.

Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to radiation environment. To prevent MCUs from causing data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but the main problem is that they would require higher delay overhead. A novel decimal matrix code (DMC) based on divide-symbol was proposed to enhance memory reliability with lower delay overhead. But DMC required more number of redundant bits. To overcome this issue Modified Decimal Matrix Code (MDMC) was introduced with less number of redundant bits. The MDMC is typically performed using reconfigurable Array Exclusive-OR Logic (ReAXL) to compute the equivalent decimal addition. The MDMC based on ReAXL dynamically reconfigured for both Encoding and decoding and hence reduced the chip area. This MDMC can be extended to 64 bit memory or 128 bit memory by implementing this in pipeline architecture.